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Si 5 7 0 / S i 5 71
P R E L I M I N A R Y DA TA S H E E T
AN Y - R A T E I 2C PROGRAMMABLE XO/VCXO
Features
Any-rate programmable output frequencies from 10 to 945 MHz and select frequencies to 1.4 GHz I2C serial interface 3rd generation DSPLL(R) with superior jitter performance 3x better frequency stability than SAW-based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available LVPECL, CMOS, LVDS, and CML outputs Industry-standard 5x7 mm package Pb-free/RoHS-compliant 1.8, 2.5, or 3.3 V supply
Si5602
Applications
SONET / SDH xDSL 10 GbE LAN / WAN Low-jitter clock generation Optical modules Clock and data recovery
Ordering Information: See page 21.
Description
The Si570 XO/SI571 VCXO utilizes Silicon Laboratories' advanced DSPLL(R) circuitry to provide a low-jitter clock at any frequency. The Si570/SI571 are user-programmable to any output frequency from 10 to 945 MHz and select frequencies to 1400 MHz with <1 ppb resolution. The device is programmed via an I2C serial interface. Unlike traditional XO/VCXOs where a different crystal is required for each output frequency, the Si57x uses one fixedfrequency crystal and a DSPLL clock synthesis IC to provide any-rate frequency operation. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems.
Pin Assignments: See page 20. (Top View)
SDA 7 NC 1 2 3 8 SCL 6 5 4 VDD
OE GND
CLK- CLK+
Functional Block Diagram
VDD CLKCLK+
Si570
SDA 7
Fixed Frequency XO Any-rate 10-1400 MHz (R) DSPLL Clock Synthesis
VC
SCL
1 2 3 8 SCL
6 5 4
VDD
SDA
OE GND
CLK- CLK+
SI571 only ADC
OE VC
GND
SI571
Si570/SI571
Rev. 0.3 6/07
Copyright (c) 2007 by Silicon Laboratories
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si570/SI571
2
Rev. 0.3
Si570/SI571 TABLE O F CONTENTS
Section Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1. Frequency Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2. Frequency Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. SI571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
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1. Detailed Block Diagrams
VDD GND
fXTAL
+
RFREQ
M
DCO
fosc
/HS_DIV
/N1
CLKOUT+ CLKOUT-
Frequency Control
OE SDA SCL
Control Interface NVM RAM
Figure 1. Si570 Detailed Block Diagram
VDD
GND
fXTAL
VC
ADC
VCADC
+
RFREQ
M
DCO
fosc
/HS_DIV
/N1
CLKOUT+ CLKOUT-
Frequency Control
OE SDA SCL
Control Interface NVM RAM
Figure 2. SI571 Detailed Block Diagram
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2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
1
Symbol VDD
Test Condition 3.3 V option 2.5 V option 1.8 V option Output enabled LVPECL CML LVDS CMOS TriState mode VIH VIL
Min 2.97 2.25 1.71 -- -- -- -- -- 0.75 x VDD -- -40
Typ 3.3 2.5 1.8 120 108 99 90 60 -- -- --
Max 3.63 2.75 1.89 130 117 108 98 75 -- 0.5 85
Units V
Supply Voltage
Supply Current
IDD
mA
Output Enable (OE)2 Operating Temperature Range TA
V C
Notes: 1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 21 for further details. 2. OE pin includes a 17 k pullup resistor to VDD or a 17 k pulldown to GND depending on the OE polarity specified in the part number. See "7. Ordering Information" on page 21.
Table 2. VC Control Voltage Input
Parameter Symbol Test Condition Min Typ 33 45 90 135 180 356 1 5 10.0 -- VDD/2 Max Units
Control Voltage Tuning Slope1,2,3
KV
VC 10 to 90% of VDD
--
--
ppm/V
Control Voltage Linearity4 Modulation Bandwidth VC Input Impedance Nominal Control Voltage Control Voltage Tuning Range
LVC BW ZVC VCNOM VC
BSL Incremental
-5 -10 9.3 500
+5 +10 10.7 -- -- VDD
% kHz k V V
@ fO
-- 0
Notes: 1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 21. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application's minimum APR requirements. See "AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)" for more information. 3. KV variation is 10% of typical values. 4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope determined with VC ranging from 10 to 90% of VDD.
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Table 3. CLK Output Frequency Characteristics
Parameter Programmable Frequency Range1,2,3 Temperature Stability1,4 Symbol fO Test Condition LVPECL/LVDS/CML CMOS TA = -40 to +85 C
Frequency drift over first year Frequency drift over 15 year life Temp stability = 20 ppm Temp stability = 50 ppm
Min 10 10 -20 -50 -100
-- -- -- --
Typ -- -- -- -- --
-- -- -- --
Max 945 160 +20 +50 +100
3 10 31.5 61.5
Units MHz
ppm
ppm ppm ppm ppm
Aging
fa
Total Stability
Absolute Pull Range1,4 Power up Time5 Settling Time after Frequency Change
APR tOSC tFRQ f1 within 100 ppm of f0 f1 > 100 ppm of f0
25 -- -- --
-- -- -- --
375 10 100 10
ppm ms s ms
Notes: 1. See Section "7. Ordering Information" on page 21 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Nominal output frequency set by VCNOM = 1/2 x VDD. 4. Selectable parameter specified by part number. 5. Time from power up or tristate mode to fO.
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Table 4. CLK Output Levels and Symmetry
Parameter LVPECL Output Option1 Symbol VO
VOD VSE
Test Condition
mid-level swing (diff) swing (single-ended) mid-level swing (diff)
Min
VDD - 1.42 1.1 0.55 1.125 0.5
Typ
--
Max
VDD - 1.25 1.9 0.95 1.275 0.9
Units
V VPP VPP V VPP
-- --
1.20 0.7
LVDS Output
Option2
VO
VOD
CML Output Option2 CMOS Output Option3 Rise/Fall time (20/80%)
VO VOD VOH VOL
mid-level swing (diff) IOH = 32 mA
IOL = 32 mA
-- 0.70
0.8 x VDD
VDD - 0.75 0.95 -- -- -- 1 --
-- 1.20
VDD
V
VPP V
-- -- -- 45
0.4 350 -- 55
tR, tF
LVPECL/LVDS/CML CMOS with CL = 15 pF LVPECL: LVDS: CMOS: VDD - 1.3 V (diff) 1.25 V (diff) VDD/2
ps ns %
Symmetry (duty cycle)
SYM
Notes: 1. 50 to VDD - 2.0 V. 2. Rterm = 100 (differential). 3. CL = 15 pF
Table 5. CLK Output Phase Jitter (Si570)
Parameter Phase Jitter (RMS)* for FOUT > 500 MHz Phase Jitter (RMS)* for FOUT of 125 to 500 MHz Symbol Test Condition 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Min -- -- -- -- Typ 0.25 0.26 0.36 0.34 Max 0.40 0.37 0.50 0.42 ps Units ps
J J
12 kHz to 20 MHz (OC-48) 50 kHz to 20 MHz (OC-192)
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
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Table 6. CLK Output Phase Jitter (SI571)
Parameter Phase Jitter (RMS)1,2,3 for FOUT > 500 MHz Symbol Test Condition Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Min -- -- -- -- -- -- -- -- -- -- -- -- Typ 0.26 0.26 0.27 0.26 0.32 0.26 0.40 0.27 0.49 0.28 0.87 0.33 Max -- -- -- -- -- -- -- -- -- -- -- -- Units ps
J
Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application's minimum APR requirements. See "AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)" for more information. 3. See "AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO" for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions.
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Table 6. CLK Output Phase Jitter (SI571) (Continued)
Parameter Phase Jitter for FOUT of 125 to 500 MHz (RMS)1,2,3 Symbol Test Condition Kv = 33 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 45 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 90 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 135 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 180 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Kv = 356 ppm/V 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) Min -- -- -- -- -- -- -- -- -- -- -- -- Typ 0.37 0.33 0.37 0.33 0.43 0.34 0.50 0.34 0.59 0.35 1.00 0.39 Max -- -- -- -- -- -- -- -- -- -- -- -- Units ps
J
Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application's minimum APR requirements. See "AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)" for more information. 3. See "AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO" for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions.
Table 7. CLK Output Period Jitter
Parameter Period Jitter* Symbol JPER Test Condition RMS Peak-to-Peak Min -- -- Typ 2 14 Max -- -- Units ps
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to "AN279: Estimating Period Jitter from Phase Noise" for further information.
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Table 8. Typical CLK Output Phase Noise (Si570)
Offset Frequency (f) 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz 120.00 MHz LVDS -112 -122 -132 -137 -144 -150 n/a 156.25 MHz LVPECL -105 -122 -128 -135 -144 -147 n/a 622.08 MHz LVPECL -97 -107 -116 -121 -134 -146 -148 Units
dBc/Hz
Table 9. Typical CLK Output Phase Noise (SI571)
Offset Frequency 74.25 MHz 90 ppm/V LVPECL 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz -87 -114 -132 -142 -148 -150 n/a 491.52 MHz 45 ppm/V LVPECL -75 -100 -116 -124 -135 -146 -147 622.08 MHz 135 ppm/V LVPECL -65 -90 -109 -121 -134 -146 -147 Units
dBc/Hz
Table 10. Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Storage Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (lead-free profile) Soldering Temperature Time @ TPEAK (lead-free profile) Symbol VDD VI TS ESD TPEAK tP Rating -0.5 to +3.8 -0.5 to VDD + 0.3 -55 to +125 >2500 260 20-40 Units Volts Volts C Volts C seconds
Notes: 1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles.
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Table 11. Environmental Compliance
The Si570/571 meets the following qualification test requirements.
Parameter Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solvents
Conditions/Test Method MIL-STD-883F, Method 2002.3 B MIL-STD-883F, Method 2007.3 A MIL-STD-883F, Method 203.8 MIL-STD-883F, Method 1014.7 MIL-STD-883F, Method 2016
Table 12. Programming Constraints
(VDD = 3.3 V 10%, TA = -40 to 85 C)
Parameter
Symbol
Test Condition HS_DIV x N1 > = 6 HS_DIV x N1 = 5 N1 = 1 HS_DIV = 4 N1 = 1
Min 10 970 1.2125 -- 4850 --
Typ -- -- -- 0.09 -- --
Max 945 1134 1.4175 -- 5670 10
Unit MHz MHz GHz ppb MHz ms
Output Frequency
CKOF
M and RFREQ Value LSB Resolution Internal Oscillator Frequency Unfreeze to NewFreq Delay
MRES fOSC
114.285 MHz 3rd Overtone Crystal
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Si570/SI571
3. Functional Description
The Si570 XO and the SI571 VCXO are low-jitter, programmable oscillators ideally suited for applications requiring multiple frequencies. The Si57x can be programmed to generate any output clock rate between 10 and 1.4 GHz with <1 ppb resolution. Output jitter performance exceeds the strict requirements of highspeed communication systems including OC-48/OC192 and 10 Gigabit Ethernet. The Si57x employs Silicon Laboratories' thirdgeneration digital signal processing based phaselocked loop (DSPLL(R)) technology providing excellent jitter performance, digital programmability, and stability while requiring minimal external components. At the core of the Si57x is a digitally-controlled oscillator (DCO) based on DSPLL technology that is driven by a digital frequency control word and produces a low-jitter output clock. (See "1. Detailed Block Diagrams" on page 4.) 3.2.2. Calculating the Reference Frequency Multiplier (RFREQ) RFREQ is a binary representation of the reference frequency multiplier and is 38 bits in length. To convert from a decimal number to the binary number RFREQ must be broken into two parts: the integer portion and the fractional portion. The first 10 most-significant-bits (MSBs) of RFREQ represent the integer portion, and the lower 28 least-significant-bits (LSB's) represent the fractional portion. The integer portion can be converted directly from decimal to binary (e.g. decimal 43 = hexadecimal 02Bh--the leading nibble only occupies two bits of RFREQ). The fractional portion should be made into an integer by multiplying by 228 and truncating (or rounding) the result as follows: (e.g. 0.54587216*2^28 = 146531442.18730496; then, truncate to 146531442). The truncated value can then be converted to binary (e.g. decimal 146531442 = hexadecimal 8BBE472h). The resulting binary RFREQ for 43.54587216 is 02B8BBE472h (02Bh concatenated with 8BBE472h). 3.2.3. Programming Procedure The following steps must be followed to set a new output frequency: 1. Read the frequency configuration (RFREQ, HS_DIV, and N1) from the device after power-up or reset. 2. Calculate the actual nominal crystal frequency (fXTAL) as: (fXTAL = f0 x HS_DIV x N1)/RFREQ where f0 is the nominal output frequency. 3. Choose new output frequency (f1). 4. Choose the output dividers (HS_DIV and N1) for the new output frequency by ensuring the DCO oscillation frequency (fosc) is within the allowed internal oscillator frequency (See Table 12) where: fosc = f1 x HS_DIV x N1. 5. Calculate the new crystal frequency multiplication ratio (RFREQ1) as: fosc = fXTAL x RFREQ. 6. Freeze the DCO (bit 5 of Register 137). 7. Write the frequency configuration (RFREQ, HS_DIV, and N1). 8. Unfreeze the DCO and assert the NewFreq bit (bit 6 of Register 135) within the maximum delay specified in Table 12, "Programming Constraints," on page 11. 3.2.4. Programming Procedure Example The Si57x-EVB software can be used to generate examples as needed.
3.1. Frequency Programming Summary
The output frequency is determined by programming the output dividers (HS_DIV and N1) and the fine frequency control value (RFREQ). The value programmed into RFREQ is a high-resolution 38-bit value that adjusts the DCO frequency in a range from 4.85 to 5.67 GHz. The output of the DCO is divided down by HS_DIV and N1 to produce the desired output frequency. The 38-bit length of RFREQ provides an output frequency resolution of better than 1 ppb.
3.2. Frequency Programming Details
Programming consists of the following basic steps: deriving the actual crystal frequency, choosing new output dividers (HS_DIV & N1), calculating a new frequency multiplier (RFREQ), and writing the new frequency set into the device (HS_DIV, N1, and RFREQ). 3.2.1. Selecting the Correct Output Dividers By listing all of the combinations of HS_DIV and N1, one can choose the output divider set with the lowest power within the allowed internal oscillator frequency range as specified in Table 12. The sets of dividers should be sorted to minimize fosc for power dissipation and to minimize N1 divider's power consumption. Silicon Laboratories' Si57x software automatically provides this optimization and returns the smallest HS_DIV x N1 combination with the highest HS_DIV value.
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Si570/SI571
3.3. I2C Interface
The control interface to the Si570 is an I2C-compatible 2-wire bus for bidirectional communication. The bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both lines must be connected to the positive supply via an external pullup. Fast mode operation is supported for transfer rates up to 400 kbps as specified in the I2C-Bus Specification standard. Figure 3 shows the command format for both read and write access. Data is always sent MSB first. The timing specifications and timing diagram for the I2C bus can be found in the I2C-Bus Specification standard (fast mode operation). The device I2C address is specified in the part number.
S
Slave Address
0
A Byte Address
A
Data
A
Data
A
P
Write Command
S Slave Address 0 A Byte Address A S Slave Address 1 A Data A Data A P
Read Command Address auto incremented after each data read or write
From master to slave From slave to master A - Acknowledge (SDA LOW) S - START condition P - STOP condition
Figure 3. I2C Command Format
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Si570/SI571
4. Serial Port Registers
Note: Any register not listed here is reserved and must not be written. All bits are R/W unless otherwise noted.
Register 7 8 9 10 11 12 135 137
Name High Speed/ N1 Dividers Reference Frequency Reference Frequency Reference Frequency Reference Frequency Reference Frequency
Bit 7
Bit 6 HS_DIV[2:0]
Bit 5
Bit 4
Bit 3
Bit 2 N1[6:2]
Bit 1
Bit 0
N1[1:0]
RFREQ[37:32] RFREQ[31:24] RFREQ[23:16] RFREQ[15:8] RFREQ[7:0] RECALL Freeze DCO
Reset/Memory Control RST_REG NewFreq Freeze DCO
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Register 7. High Speed/N1 Dividers Bit Name Type Bit 7:5 Name HS_DIV[2:0] D7 D6 HS_DIV[2:0] R/W Function DCO High Speed Divider. Sets value for high speed divider that takes the DCO output fOSC as its clock input. 000 = 4 001 = 5 010 = 6 011 = 7 100 = Not used. 101 = 9 110 = Not used. 111 = 11 CLKOUT Output Divider. Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Illegal odd divider values will be rounded up to the nearest even value. The value for the N1 register can be calculated by taking the divider ratio minus one. For example, to divide by 10, write 0001001 (9 decimal) to the N1 registers. 0000000 = 1 1111111 = 27 D5 D4 D3 D2 N1[6:2] R/W D1 D0
4:0
N1[6:2]
Register 8. Reference Frequency Bit Name Type Bit 7:6 D7 N1[1:0] R/W Name N1[1:0] D6 D5 D4 D3 D2 D1 D0
RFREQ[37:32] R/W Function CLKOUT Output Divider. Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 27]. Illegal odd divider values will be rounded up to the nearest even value. The value for the N1 register can be calculated by taking the divider ratio minus one. For example, to divide by 10, write 0001001 (9 decimal) to the N1 registers. 0000000 = 1 1111111 = 27 Reference Frequency. Frequency control input to DCO.
5:0
RFREQ[37:32]
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Si570/SI571
Register 9. Reference Frequency Bit Name Type Bit 7:0 Name RFREQ[31:24] Reference Frequency. Frequency control input to DCO. D7 D6 D5 D4 D3 D2 D1 D0
RFREQ[31:24] R/W Function
Register 10. Reference Frequency Bit Name Type Bit 7:0 Name RFREQ[23:16] Reference Frequency. Frequency control input to DCO. D7 D6 D5 D4 D3 D2 D1 D0
RFREQ[23:16] R/W Function
Register 11. Reference Frequency Bit Name Type Bit 7:0 Name RFREQ[15:8] Reference Frequency. Frequency control input to DCO. D7 D6 D5 D4 D3 D2 D1 D0
RFREQ[15:8] R/W Function
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Register 12. Reference Frequency Bit Name Type Bit 7:0 Name RFREQ[7:0] Reference Frequency. Frequency control input to DCO. D7 D6 D5 D4 D3 D2 D1 D0
RFREQ[7:0] R/W Function
Register 135. Reset/Memory Control Bit Name Type D7 RST_REG R/W D6 NewFreq R/W D5 D4 D3 N/A R/W D2 D1 D0 RECALL R/W
Reset settings = 00xx xx00 Bit 7 Name RST_REG Function Internal Reset. 0 = Normal operation. 1 = Reset of all internal logic. Output tristated during reset. Upon completion of internal logic reset, RST_REG is internally reset to zero. New frequency applied. Alerts the DSPLL that a new frequency configuration has been applied. This bit will clear itself when the new frequency is applied. Always zero. Recall NVM into RAM. 0 = No operation. 1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.
6
NewFreq
5:1 0
N/A RECALL
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Register 137. Freeze DCO Bit Name Type Reset settings = 00xx xx00 Bit 7:6 5 4:0 Name Reserved Freeze DCO Reserved Freeze DCO. Freezes the DSPLL so the frequency configuration can be modified. Function D7 D6 D5 Freeze DCO R/W D4 D3 D2 D1 D0
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5. Si570 (XO) Pin Descriptions
(Top View)
SDA 7 NC 1 2 3 8 SCL 6 5 4 VDD
OE GND
CLK- CLK+
Table 13. Si570 Pin Descriptions
Pin 1 2 3 4 5 6 7 8 Name NC OE GND CLK+ CLK- (N/A for CMOS) VDD SDA SCL Type N/A Input Ground Output Output Power Bidirectional Open Drain Input No Connect. Output Enable: See "7. Ordering Information" on page 21. Electrical and Case Ground. Oscillator Output. Complementary Output (N/C for CMOS). Power Supply Voltage. I2C Serial Data. I2C Serial Clock. Function
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6. SI571 (VCXO) Pin Descriptions
(Top View)
SDA 7 VC 1 2 3 8 SCL 6 5 4 VDD
OE GND
CLK- CLK+
Table 14. SI571 Pin Descriptions
Pin 1 2 3 4 5 6 7 8 Name VC OE GND CLK+ CLK- (N/A for CMOS) VDD SDA SCL Type Analog Input Input Ground Output Output Power Bidirectional Open Drain Input Control Voltage Output Enable: See "7. Ordering Information" on page 21. Electrical and Case Ground Oscillator Output Complementary Output (N/C for CMOS) Power Supply Voltage I2C Serial Data I2C Serial Clock Function
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7. Ordering Information
The Si570/SI571 supports a wide variety of options including frequency range, start-up frequency, temperature stability, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si570/SI571 at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si570/SI571 XO/ VCXO series is supplied in an industry-standard, RoHS compliant, Pb-free, 8-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
57x X X X XXX XXX D G R
R = Tape & Reel Blank = Trays 570 Programmable XO Product Family 571 Programmable VCXO Product Family Operating Temp Range (C) G -40 to +85 C Device Revision Letter Six-Digit Start-up Frequency/I2C Address Designator The Si57x supports a user-defined start-up frequency within the following bands of frequencies: 10-945 MHz, 970-1134 MHz, and 1213-1417 MHz. The start-up frequency must be in the same frequency range as that specified by the Frequency Grade 3rd option code. The Si57x supports a user-defined I2C 7-bit address. Each unique start-up frequency/I2C address combination is assigned a six-digit numerical code. This code can be requested during the part number request process. Refer to www.silabs.com/VCXOPartNumber to request an Si57x part number. 3rd Option Code Frequency Grade Code A B C Frequency Range Supported (MHz) 10-945, 970-1134, 1213-1417.5 10-810 10-215
1st Option Code A B C D E F G H J K M N P Q R S T U V W VDD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format Output Enable Polarity LVPECL High LVDS High CMOS High CML High LVPECL High LVDS High CMOS High CML High CMOS High CML High LVPECL Low LVDS Low CMOS Low CML Low LVPECL Low LVDS Low CMOS Low CML Low CMOS Low CML Low
Si570
2nd Option Code Code Temperature Stability (ppm, max, ) Total Stablility (ppm, max, ) A 50 61.5 B 20 31.5 2nd Option Code Temperature Tuning Slope Minimum APR Stability Kv (ppm) for VDD @ Code ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V A 100 180 100 75 25 B 100 90 30 Note 6 Note 6 C 50 180 150 125 75 D 50 90 80 30 25 E 20 45 25 Note 6 Note 6 F 50 135 100 75 50 G 20 356 375 300 235 H 20 180 185 145 105 J 20 135 130 104 70 K 100 356 295 220 155 M 20 33 12 Note 6 Note 6 Notes: 1. For best jitter and phase noise performance, always choose the smallest Kv that meets the application's minimum APR requirements. Unlike SAW-based solutions which require higher higher Kv values to account for their higher temperature dependence, the Si55x series provides lower Kv options to minimize noise coupling and jitter in realworld PLL designs. See AN255 and AN266 for more information. 2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an APR of 25 ppm is able to lock to a clock with a 25 ppm stability over 15 years over all operating conditions. 3. Nominal Pull range () = 0.5 x VDD x tuning slope. 4. Nominal Absolute Pull Range (APR) = Pull range - stability - lifetime aging = 0.5 x VDD x tuning slope - stability - 10 ppm 5. Minimum APR values noted above include worst case values for all parameters. 6. Combination not available.
Note: CMOS available to 160 MHz.
SI571
Figure 4. Part Number Convention
Rev. 0.3
21
Si570/SI571
8. Si57x Mark Specification
Figure 5 illustrates the mark specification for the Si57x. Table 15 lists the line information.
6
5
4
SiLabs 123
1234567890 R T T T T Y WW+
1 2
Figure 5. Mark Specification Table 15. Si57x Top Mark Description
Line 1 2 3 Position 1-10 1-10 Trace Code Position 1 Position 2 Position 3-6 Position 7 Position 8-9 Position 10 Pin 1 orientation mark (dot) Product Revision (D) Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7) Calendar Work Week number (1-53), to be assigned by assembly site "+" to indicate Pb-Free and RoHS-compliant Description "SiLabs"+ Part Family Number, 5xx (First 3 characters in part number) Si570, SI571: Option1 + Option2 + Option3 + ConfigNum(6) + Temp
3
22
Rev. 0.3
Si570/SI571
9. Outline Diagram and Suggested Pad Layout
Figure 6 illustrates the package details for the Si570/SI571. Table 16 lists the values for the dimensions shown in the illustration.
Figure 6. Si570/SI571 Outline Diagram Table 16. Package Diagram Dimensions (mm)
Dimension A b c d D D1 e E E1 L M S R aaa bbb ccc ddd -- -- -- -- 4.30 1.07 0.8 6.10 0.97 Min 1.45 1.2 Nom 1.65 1.4 0.60 TYP 1.17 7.00 BSC 6.2 2.54 BSC 5.00 BSC 4.40 1.27 1.0 1.815 BSC 0.7 REF -- -- -- -- 0.15 0.15 0.10 0.10 4.50 1.47 1.2 6.30 1.37 Max 1.85 1.6
Rev. 0.3
23
Si570/SI571
10. 8-Pin PCB Land Pattern
Figure 7 illustrates the 8-pin PCB land pattern for the Si570/SI571. Table 17 lists the values for the dimensions shown in the illustration.
Figure 7. Si570/SI571 PCB Land Pattern Table 17. PCB Land Pattern Dimensions (mm)
Dimension D2 D3 e E2 GD GE VD VE X1 X2 Y1 Y2 ZD ZE -- -- 0.84 2.00 8.20 REF 7.30 REF 1.70 TYP 1.545 TYP 2.15 REF 1.3 REF 6.78 6.30 Min 5.08 REF 5.705 REF 2.54 BSC 4.20 REF -- -- Max
Note: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design follows IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm).
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Rev. 0.3
Si570/SI571
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated " Description" on page 1. Updated "1. Detailed Block Diagrams" on page 4 for both XO and VCXO. Updated the Nominal Control Voltage in Table 2, "VC Control Voltage Input," on page 5. Updated tables to reflect slight performance differences between Si570 and SI571. Added detail to the "3.2. Frequency Programming Details" on page 12. Revised "3.2.3. Programming Procedure" on page 12.
Procedure now requires use of two frequency configuration register sets.
Procedure now recommends disabling output at powerup to protect equipment not expecting the default output frequency. Added second frequency configuration register set to the register tables. Added frequency configuration select register. Updated "7. Ordering Information" on page 21 to be consistent with the Si55x series devices.
Revision 0.2 to Revision 0.3
Updated Table 1, "Recommended Operating Conditions," on page 5.
Device maintains stable operation over -40 to +85 C operating temperature range. Supply current specifications updated.
Updated Table 4, "CLK Output Levels and Symmetry," on page 7.
Updated LVDS differential peak-peak swing specifications.
Updated Table 5, "CLK Output Phase Jitter (Si570)," on page 7. Updated Table 6, "CLK Output Phase Jitter (SI571)," on page 8. Updated Table 7, "CLK Output Period Jitter," on page 9.
Revised period jitter specifications.
Updated Table 10, "Absolute Maximum Ratings," on page 10 to reflect the soldering temperature time at 260 C is 20-40 sec per JEDEC J-STD-020C. Updated device programming procedure in Section "3.2.3. Programming Procedure" on page 12. Updated "7. Ordering Information" on page 21.
Changed ordering instructions to revision D.
Added "8. Si57x Mark Specification" on page 22.
Rev. 0.3
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Si570/SI571
CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Rev. 0.3

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